Models & Optimisation and Mathematical Analysis Journal
Volume 1, Numéro 1, Pages 66-71
2012-12-17
Implementation Of A Real-time Signal Processing Application Using Partial Dynamic Reconfiguration In Fpga
Authors : Touiza Maamar . Messaoudi Kamel . Bourennane El-bay . Guessoum Abderrezak .
Abstract
Reconfigurable devices, such as modern FPGA provide advanced capabilities which allow the creation of embedded systems on single chips (SoC). One of the most challenging opportunities provided by this kind of devices is the ability to dynamically and partially reconfigure themselves. It consists in the modification of a portion of the circuitry mapped on the FPGA while the system is running. This ability allows development of flexible systems that can deal with changes in the requirements, standards and operational conditions. This paper presents partially reconfigurable FIR filter design that employs dynamic partial reconfiguration. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of many response FIR filters using Xilinx FPGA. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various types. This FIR filter design method shows the good area efficiency and flexibility by using the dynamic partial reconfiguration method.
Keywords
Dynamic Partial Reconfiguration, FPGA, Signal Processing.
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